Freescale Semiconductor ColdFire MCF52210 - Manual (Page 564)

Register Memory Map Quick Reference
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
A-10 Freescale Semiconductor
IPSBAR + 0x0C6D Interrupt Control Register 0-45 ICR045 8
IPSBAR + 0x0C6E Interrupt Control Register 0-46 ICR046 8
IPSBAR + 0x0C6F Interrupt Control Register 0-47 ICR047 8
IPSBAR + 0x0C70 Interrupt Control Register 0-48 ICR048 8
IPSBAR + 0x0C71 Interrupt Control Register 0-49 ICR049 8
IPSBAR + 0x0C72 Interrupt Control Register 0-50 ICR050 8
IPSBAR + 0x0C73 Interrupt Control Register 0-51 ICR051 8
IPSBAR + 0x0C74 Interrupt Control Register 0-52 ICR052 8
IPSBAR + 0x0C75 Interrupt Control Register 0-53 ICR053 8
IPSBAR + 0x0C76 Interrupt Control Register 0-54 ICR054 8
IPSBAR + 0x0C77 Interrupt Control Register 0-55 ICR055 8
IPSBAR + 0x0C78 Interrupt Control Register 0-56 ICR056 8
IPSBAR + 0x0C79 Interrupt Control Register 0-57 ICR057 8
IPSBAR + 0x0C7A Interrupt Control Register 0-58 ICR058 8
IPSBAR + 0x0C7B Interrupt Control Register 0-59 ICR059 8
IPSBAR + 0x0C7C Interrupt Control Register 0-60 ICR060 8
IPSBAR + 0x0C7D Interrupt Control Register 0-61 ICR061 8
IPSBAR + 0x0C7E Interrupt Control Register 0-62 ICR062 8
IPSBAR + 0x0C7F Interrupt Control Register 0-63 ICR063 8
IPSBAR + 0x0CE0 Software Interrupt Acknowledge Register 0 SWACK0 8
IPSBAR + 0x0CE4 Level 1 Interrupt Acknowledge Register 0 L1IACK0 8
IPSBAR + 0x0CE8 Level 2 Interrupt Acknowledge Register 0 L2IACK0 8
IPSBAR + 0x0CEC Level 3 Interrupt Acknowledge Register 0 L3IACK0 8
IPSBAR + 0x0CF0 Level 4 Interrupt Acknowledge Register 0 L4IACK0 8
IPSBAR + 0x0CF4 Level 5 Interrupt Acknowledge Register 0 L5IACK0 8
IPSBAR + 0x0CF8 Level 6 Interrupt Acknowledge Register 0 L6IACK0 8
IPSBAR + 0x0CFC Level 7 Interrupt Acknowledge Register 0 L7IACK0 8
IPSBAR + 0x0FE4 Global Level 1 Interrupt Acknowledge Register GL1IACK 8
IPSBAR + 0x0FE8 Global Level 2 Interrupt Acknowledge Register GL2IACK 8
IPSBAR + 0x0FEC Global Level 3 Interrupt Acknowledge Register GL3IACK 8
IPSBAR + 0x0FF0 Global Level 4 Interrupt Acknowledge Register GL4IACK 8
IPSBAR + 0x0FF4 Global Level 5 Interrupt Acknowledge Register GL5IACK 8
IPSBAR + 0x0FF8 Global Level 6 Interrupt Acknowledge Register GL6IACK 8
Table A-3. Register Memory Map (continued)
Address Name Mnemonic Size (bits)