Freescale Semiconductor ColdFire MCF52210 - Manual (Page 247)

Universal Serial Bus, OTG Capable Controller
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-19
15.4.1.11 Error Interrupt Status Register (ERR_STAT)
The Error Interrupt Status Register contains enable bits for each of the error sources within the USB
Module. Each of these bits are qualified with their respective error enable bits (see
Section 15.4.1.12,
“Error Interrupt Enable Register (ERR_ENB) ”). All bits of this Register are logically OR’d together and
the result placed in the ERROR bit of the INT_STAT register. After an interrupt bit has been set it may
only be cleared by writing a one to the respective interrupt bit. Each bit is set as soon as the error conditions
is detected. Therefore, the interrupt does not typically correspond with the end of a token being processed.
This register contains the value of 0x00 after a reset.
Figure 15-17 shows the ERR_STAT register.
IPSBAR
Offset: 0x1C_0088 (ERR_STAT) Access: User read/write
7 6 5 4 3 2 1 0
R
BTS_ERR
Reserved
DMA_ERR BTO_ERR DFN8 CRC16 CRC5_EOF PID_ERR
W –
Reset: 0 0 0 0 0 0 0 0
Figure 15-17. Error Interrupt Status Register
Table 15-21. ERR_STAT Field Descriptions
Field Description
7
BTS_ERR
This bit is set when a bit stuff error is detected. If set, the corresponding packet is rejected due to the error.
6 Reserved
5
DMA_ERR
This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the
bus before it needs to receive or transmit data. If processing a TX transfer this would cause a transmit data
underflow condition. If processing a RX transfer this would cause a receive data overflow condition. This
interrupt is useful when developing device arbitration hardware for the microprocessor and the USB Module to
minimize bus request and bus grant latency.
This bit is also set if a data packet to or from the host is larger than the buffer size allocated in the BDT. In this
case the data packet is truncated as it is put into buffer memory.
4
BTO_ERR
This bit is set when a bus turnaround timeout error occurs. The USB Module contains a bus turnaround timer
that keeps track of the amount of time elapsed between the token and data phases of a SETUP or OUT TOKEN
or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted from the previous
EOP before a transition from IDLE, a bus turnaround timeout error occurs.
3
DFN8
This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data fields
be an integral number of bytes. If the data field was not an integral number of bytes, this bit is set.
2
CRC16
This bit is set when a data packet is rejected due to a CRC16 error.
1
CRC5_EOF
This error interrupt has two functions.
When the USB Module is operating in peripheral mode (HOST_MODE_EN=0), this interrupt detects CRC5
errors in the token packets generated by the host. If set the token packet was rejected due to a CRC5 error.
When the USB Module is operating in host mode (HOST_MODE_EN=1), this interrupt detects End Of Frame
(EOF) error conditions. This occurs when the USB Module is transmitting or receiving data and the SOF counter
reaches zero. This interrupt is useful when developing USB packet scheduling software to ensure that no USB
transactions cross the start of the next frame.
0
PID_ERR
This bit is set when the PID check field fails.