Freescale Semiconductor ColdFire MCF52210 - Manual (Page 448)

Analog-to-Digital Converter (ADC)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
26-12 Freescale Semiconductor
Table 26-11. ADSTAT Field Descriptions
Field Description
15
CIP0
Conversion in Progress 0 bit. This bit indicates when a scan is in progress. This bit supports any sequential
scan or parallel scan with SIMULT equaling 1. When executing a parallel scan with SIMULT equaling 0, this
bit services the scan of converter A, and the CIP1 bit services the scan of converter B.
0 Idle state
1 A scan cycle is in progress (the ADC ignores all sync pulses or start commands)
14
CIP1
Conversion in Progress 1 bit. This refers only to a B converter scan in non-simultaneous (SIMULT=0) parallel
scan modes.
0 Idle state
1 A scan cycle is in progress (the ADC ignores all sync pulses or start commands)
13 Reserved, should be cleared.
12
EOSI1
End of Scan Interrupt 1 bit. This bit indicates whether a scan of analog inputs has been completed since the
last read of ADSTAT or a reset. The EOSI1 bit is cleared by writing a 1 to it. This bit cannot be set by software.
In looping scan modes, this interrupt is triggered at the completion of each iteration of the loop. This interrupt
is triggered only by the completion of a B converter scan in non-simultaneous (SIMULT=0) parallel scan
modes. In this case the EOSI0 interrupt is triggered when converter A completes its scan.
0 A scan cycle has not been completed, no end of scan IRQ pending
1 A scan cycle has been completed, end of scan IRQ pending
11
EOSI0
End of Scan Interrupt 0 bit. This bit indicates whether a scan of analog inputs has been completed since the
last read of ADSTAT or a reset. The EOSI0 bit is cleared by writing a 1 to it. This bit cannot be set by software.
EOSI0 is the preferred bit to poll for scan completion if interrupts are not enabled.
In looping scan modes, this interrupt is triggered at the completion of each iteration of a loop.
This interrupt is triggered upon the completion of any sequential scan or parallel scan with
SIMULT equaling 1. When executing parallel scans with SIMULT equaling 0, this interrupt is triggered when
converter A completes its scan while the EOSI1 interrupt services converter B.
0 A scan cycle has not been completed, no end of scan IRQ pending
1 A scan cycle has been completed, end of scan IRQ pending
10
ZCI
Zero Crossing Interrupt bit. This bit is asserted at the completion of an individual conversion experiencing a
zero crossing enabled in the ADC zero crossing control (ADZCC) register. The bit is set as soon as an
enabled zero crossing event occurs rather than at the end of the ADC scan. ZCI is cleared by writing 1 to all
active ADZCSTAT[ZCS] bits.
0 No ZCI interrupt request
1 Zero crossing encountered; IRQ pending if CTRL1[ZCIE] is set
9
LLMTI
Low Limit Interrupt bit. If any low limit register (ADLLMTn) is enabled by having a value other than 0x0, low
limit checking is enabled. This bit is set at the completion of an individual conversion which may or may not
be the end of a scan. It is cleared by writing 1 to all active ADLSTAT[LLS] bits.
0 No low limit interrupt request
1 Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set