Freescale Semiconductor ColdFire MCF52210 - Manual (Page 434)

I 2 C Interface
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
25-14 Freescale Semiconductor
may need to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with
the following instructions.
The following example signals START and transmits the first byte of data (slave address):
1. Check I2SR[IBB]. If it is set, wait until it is clear.
2. After cleared, set to transmit mode by setting I2CR[MTX].
3. Set master mode by setting I2CR[MSTA]. This generates a START condition.
4. Transmit the calling address via the I2DR.
5. Check I2SR[IBB]. If it is clear, wait until it is set and go to step #1.
25.4.3 Post-Transfer Software Response
Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is finished.
I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during initialization by
setting I2CR[IIEN]. Software must first clear I2SR[IIF] in the interrupt routine. Reading from I2DR in
receive mode or writing to I2DR in transmit mode can clear I2SR[ICF].
Software can service the I
2
C I/O in the main program by monitoring the IIF bit if the interrupt function is
disabled. Polling should monitor IIF rather than ICF, because that operation is different when arbitration
is lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the
address is sent. If master receive mode is required, I2CR[MTX] should be toggled.
During slave-mode address cycles (I2SR[IAAS] = 1), I2SR[SRW] is read to determine the direction of the
next transfer. MTX is programmed accordingly. For slave-mode data cycles (IAAS = 0), SRW is invalid.
MTX should be read to determine the current transfer direction.
The following is an example of a software response by a master transmitter in the interrupt routine (see
Figure 25-14 ).
1. Clear the I2CR[IIF] flag.
2. Check if acknowledge has been received, I2SR[RXAK].
3. If no ACK, end transmission. Else, transmit next byte of data via I2DR.
25.4.4 Generation of STOP
A data transfer ends when the master signals a STOP, which can occur after all data is sent, as in the
following example.
1. Check if acknowledge has been received, I2SR[RXAK]. If no ACK, end transmission and go to
step #5.
2. Get value from transmitting counter, TXCNT. If no more data, go to step #5.
3. Transmit next byte of data via I2DR.
4. Decrement TXCNT and go to step #1
5. Generate a stop condition by clearing I2CR[MSTA].