Freescale Semiconductor ColdFire MCF52210 - Manual (Page 114)

Clock Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
6-20 Freescale Semiconductor
6.8.4.3 Voltage Control Output (VCO)
The voltage across the loop filter controls the frequency of the VCO output. The frequency-to-voltage
relationship (VCO gain) is positive, and the output frequency is four times the target system frequency.
6.8.4.4 Multiplication Factor Divider (MFD)
When the PLL is not in 1:1 PLL mode, the MFD divides the output of the VCO and feeds it back to the
PFD. The PFD controls the VCO frequency via the charge pump and loop filter such that the reference and
feedback clocks have the same frequency and phase. Thus, the frequency of the input to the MFD, which
is also the output of the VCO, is the reference frequency multiplied by the same amount that the MFD
divides by. For example, if the MFD divides the VCO frequency by six, the PLL is frequency locked when
the VCO frequency is six times the reference frequency. The presence of the MFD in the loop allows the
PLL to perform frequency multiplication, or synthesis.
In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is one.
6.8.4.5 PLL Lock Detection
The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when
frequency lock is achieved. Phase lock is inferred by the frequency relationship, but is not guaranteed. The
LOCK flag in the SYNSR reflects the PLL lock status. A sticky lock flag, LOCKS, is also provided.
The lock detect function uses two counters: one is clocked by the reference, and the other is clocked by
the PLL feedback. When the reference counter has counted N cycles, its count is compared to that of the
feedback counter. If the feedback counter has also counted N cycles, the process is repeated for N + K
counts. Then, if the two counters continue to match, the lock criteria is relaxed by 1/2 and the system is
notified that the PLL has achieved frequency lock.
After lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using
the alternate count and compare process. If the counters do not match at any comparison time, then the
LOCK flag is cleared to indicate that the PLL has lost lock. At this point, the lock criteria is tightened and
the lock detect process is repeated.
The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL tries to
lock. Alternating between tight and relaxed lock criteria prevents the lock detect function from randomly
toggling between locked and non-locked status due to phase sensitivities.
Figure 6-13 shows the sequence
for detecting locked and non-locked conditions.
In external clock mode, the PLL is disabled and cannot lock.