18 gpt port data register (gptport), 19 gpt port data direction register (gptddr), 7 functional description – Freescale Semiconductor ColdFire MCF52210 User Manual
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General Purpose Timer Module (GPT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
21-16
Freescale Semiconductor
21.6.18 GPT Port Data Register (GPTPORT)
21.6.19 GPT Port Data Direction Register (GPTDDR)
21.7
Functional Description
The general purpose timer (GPT) module is a 16-bit, 4-channel timer with input capture and output
compare functions and a pulse accumulator.
IPSBAR
Offset: 0x1A_001D (GPTPORT)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
PORTT
W
Reset:
0
0
0
0
0
0
0
0
Figure 21-20. GPT Port Data Register (GPTPORT)
Table 21-21. GPTPORT Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
PORTT
GPT port input capture/output compare data. Data written to GPTPORT is buffered and drives the pins only when
they are configured as general-purpose outputs.
Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1) reads the latched value. Writing
to a pin configured as a GPT output does not change the pin state. These bits are read anytime (read pin state when
corresponding PORTTn bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write anytime.
IPSBAR
Offset: 0x1A_001E (GPTDDR)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
DDRT
W
Reset:
0
0
0
0
0
0
0
0
Figure 21-21. GPT Port Data Direction Register (GPTDDR)
Table 21-22. GPTDDR Field Descriptions
Bit(s)
Name
Description
7–4
—
Reserved, should be cleared.
3–0
DDRT
Control the port logic of PORTTn. Reset clears the PORTTn data direction register,
configuring all GPT port pins as inputs. These bits are read anytime, write anytime.
1 Corresponding pin configured as output
0 Corresponding pin configured as input