Freescale Semiconductor ColdFire MCF52210 User Manual

Page 296

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ColdFire Flash Module (CFM)

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

18-6

Freescale Semiconductor

The CFM contains a set of control and status registers located at the register base address as defined by the
system level configuration. A summary of the CFM registers is given in

Table 18-3

.

Table 18-2. FLASHBAR Field Descriptions

Bits

Name

Description

31–19

BA[31:18]

Base Address Field. Defines the 0-modulo-512K base address of the flash
module. By programming this field, the flash may be located on any 512-Kbyte
boundary within the processor’s four gigabyte address space.

18–9

Reserved, should be cleared.

8

WP

Write Protect. Write only. Allows only read accesses to the flash. When this bit is
set, any attempted write access generates an access error exception to the
ColdFire processor core.
0 Allows read and write accesses to the flash module
1 Allows only read accesses to the flash module

7–6

Reserved, should be cleared.

5–1

C/I, SC, SD, UC,

UD

Address Space Masks (ASn).
These five bit fields allow certain types of accesses to be masked or inhibited from
accessing the flash module. The address space mask bits are:

C/I

CPU space/interrupt acknowledge cycle mask

SC

Supervisor code address space mask

SD

Supervisor data address space mask

UC

User code address space mask

UD

User data address space mask

For each address space bit:
0 An access to the flash module can occur for this address space
1 Disable this address space from the flash module. If a reference using this

address space is made, it is inhibited from accessing the flash module, and is
processed like any other non-flash reference.

These bits are useful for power management as detailed in

Chapter 8, “Power

Management

.

0

V

Valid. When set, this bit enables the flash module; otherwise, the module is
disabled.
0 Contents of FLASHBAR are not valid
1 Contents of FLASHBAR are valid

Table 18-3. CFM Register Address Map

IPSBAR Offset

Register Bits

31 - 24

23 - 16

15 - 8

7 - 0

0x1D_0000

CFMMCR

CFMCLKD

RESERVED

1

0x1D_0004

RESERVED

1

0x1D_0008

CFMSEC

0x1D_000C

RESERVED

1

0x1D_0010

CFMPROT

0x1D_0014

CFMSACC

0x1D_0018

CFMDACC

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