Freescale Semiconductor ColdFire MCF52210 - Manual (Page 238)

Universal Serial Bus, OTG Capable Controller
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
15-10 Freescale Semiconductor
The following sections provide details about the registers in the USB OTG memory map.
15.4.1 Capability Registers
The capability registers specify the software limits, restrictions, and capabilities of the host/device
controller implementation. Most of these registers are defined by the EHCI specification. Registers that
are not defined by the EHCI specification are noted in their descriptions.
15.4.1.1 Peripheral ID Register (PER_ID)
The Peripheral ID Register reads back the value of 0x04. This value is defined for the USB Peripheral.
Figure 15-7 shows the PER_ID register.
IPSBAR + 0x1C_00A4 Frame Number Register High FRM_NUMH 8
IPSBAR + 0x1C_00A8 Token Register TOKEN 8
IPSBAR + 0x1C_00AC SOF Threshold Register SOF_THLD 8
IPSBAR + 0x1C_00B0 BDT Page Register 2 BDT_PAGE_02 8
IPSBAR + 0x1C_00B4 BDT Page Register 3 BDT_PAGE_03 8
IPSBAR + 0x1C_00C0 Endpoint Control Register 0 ENDPT0 8
IPSBAR + 0x1C_00C4 Endpoint Control Register 1 ENDPT1 8
IPSBAR + 0x1C_00C8 Endpoint Control Register 2 ENDPT2 8
IPSBAR + 0x1C_00CC Endpoint Control Register 3 ENDPT3 8
IPSBAR + 0x1C_00D0 Endpoint Control Register 4 ENDPT4 8
IPSBAR + 0x1C_00D4 Endpoint Control Register 5 ENDPT5 8
IPSBAR + 0x1C_00D8 Endpoint Control Register 6 ENDPT6 8
IPSBAR + 0x1C_00DC Endpoint Control Register 7 ENDPT7 8
IPSBAR + 0x1C_00E0 Endpoint Control Register 8 ENDPT8 8
IPSBAR + 0x1C_00E4 Endpoint Control Register 9 ENDPT9 8
IPSBAR + 0x1C_00E8 Endpoint Control Register 10 ENDPT10 8
IPSBAR + 0x1C_00EC Endpoint Control Register 11 ENDPT11 8
IPSBAR + 0x1C_00F0 Endpoint Control Register 12 ENDPT12 8
IPSBAR + 0x1C_00F4 Endpoint Control Register 13 ENDPT13 8
IPSBAR + 0x1C_00F8 Endpoint Control Register 14 ENDPT14 8
IPSBAR + 0x1C_00FC Endpoint Control Register 15 ENDPT15 8
IPSBAR + 0x1C_0100 USB Control Register USB_CTRL 8
IPSBAR + 0x1C_0104 USB OTG Observe Register USB_OTG_OBSERVE 8
IPSBAR + 0x1C_0108 USB OTG Control Register USB_OTG_CONTROL 8
Table 15-4. USB Interface Memory Map (continued)
Address Register Acronym Bits