Freescale Semiconductor ColdFire MCF52210 - Manual (Page 184)

System Control Module (SCM)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
12-8 Freescale Semiconductor
12.5.5 Core Watchdog Service Register (CWSR)
The software watchdog service sequence must be performed using the CWSR as a data register to prevent
a CWT time-out. The service sequence requires two writes to this data register: first a write of 0x55
followed by a write of 0xAA. Both writes must be performed in this order prior to the CWT time-out, but
any number of instructions or accesses to the CWSR can be executed between the two writes. If the CWT
has already timed out, writing to this register has no effect in negating the CWT interrupt.
Figure 12-5
illustrates the CWSR. At system reset, the contents of CWSR are uninitialized.
Table 12-6. CWCR Field Description
Field Description
7
CWE
Core watchdog enable.
0 SWT disabled.
1 SWT enabled.
6
CWRI
Core watchdog interrupt select.
0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for the CWT is
programmed in the interrupt control register 8 (ICR8) of INTC0.
1 Reserved. If a one is written undetermined behavior results.
Note: If a core reset is required, the watchdog interrupt should set the soft reset bit in the interrupt controller.
5–3
CWT[2:0]
Core watchdog timing delay. These bits select the timeout period for the CWT as shown in the following table. At
system reset, the CWT field is cleared signaling the minimum time-out period but the watchdog is disabled
(CWCR[CWE] = 0). the following table shows the core watchdog timer delay.
2
CWTA
Core watchdog transfer acknowledge enable.
0 CWTA Transfer acknowledge disabled.
1 CWTA Transfer Acknowledge enabled. After one CWT time-out period of the unacknowledged assertion of the
CWT interrupt, the transfer acknowledge asserts, which allows CWT to terminate a bus cycle and allow the
interrupt acknowledge to occur.
1
CWTAVA
L
Core watchdog transfer acknowledge valid.
0 CWTA Transfer Acknowledge has not occurred.
1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.
0
CWTIF
Core watchdog timer interrupt flag.
0 CWT interrupt has not occurred
1 CWT interrupt has occurred. Write a 1 to clear the interrupt request.
CWT [2:0] CWT Time-Out Period
000 2
9
Bus clock frequency
001 2
11
Bus clock frequency
010 2 13 Bus clock frequency
011 2 15 Bus clock frequency
100 2 19 Bus clock frequency
101 2 23 Bus clock frequency
110 2 27 Bus clock frequency
111 2 31 Bus clock frequency