Chapter 6 clock module, 1 introduction, 2 features – Freescale Semiconductor ColdFire MCF52210 User Manual

Page 95: 3 modes of operation, 1 backup watchdog timer mode, Chapter 6, Clock module, Introduction -1, Features -1, Modes of operation -1

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MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor

6-1

Chapter 6
Clock Module

6.1

Introduction

The clock module allows the device to be configured for one of several clocking methods. Clocking modes
include internal phase-locked loop (PLL) clocking with an external clock reference or an external crystal
reference supported by an internal crystal amplifier. The PLL can also be disabled and an external
oscillator can be used to clock the device directly. The clock module contains the following:

Crystal amplifier and oscillator (OSC)

Phase-locked loop (PLL)

Reduced frequency divider (RFD)

Status and control registers

Control logic

Real-time clock (RTC) oscillator

6.2

Features

Features of the clock module include the following:

1- to 48-MHz crystal, 8-MHz on-chip relaxation oscillator, or external oscillator reference options

2- to 10-MHz reference crystal oscillator for normal PLL mode

External RTC/backup oscillator (nominal frequency 32.768 kHz)

System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator

Support for low-power modes

Separate clock out signal

2

n

(0

≤ n ≤ 15) low-power divider for extremely low frequency operation

6.3

Modes of Operation

The clock module can be operated in backup watchdog timer mode, RTC mode, normal PLL mode
(default), 1:1 PLL mode, or external clock mode (PLL disabled).

6.3.1

Backup Watchdog Timer Mode

In this mode, the backup watchdog timer is disabled after POR (power on reset), and the clock input to this
timer is the system clock. The selection of the clock source for the secondary watchdog timer module can
occur only once per POR. Thus, if the relaxation oscillator is selected as the timer’s input source,
subsequent attempts to select the relaxation oscillator as the system clock’s source are blocked until the

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