Freescale Semiconductor ColdFire MCF52210 - Manual (Page 177)

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-1
Chapter 12
System Control Module (SCM)
12.1 Introduction
This section details the functionality of the system control module (SCM) that provides the programming
model for the system access control unit (SACU), system bus arbiter, 32-bit core watchdog timer (CWT),
and system control registers and logic. Specifically, the system control includes the internal peripheral
system (IPS) base address register (IPSBAR), the processor’s dual-port RAM base address register
(RAMBAR), and system control registers that include the core watchdog timer control.
12.2 Overview
The SCM provides the control and status for a variety of functions including base addressing and address
space masking for the IPS peripherals and resources (IPSBAR) and the ColdFire core memory spaces
(RAMBAR). The CPU core supports two memory banks, one for the internal SRAM and the other for the
internal flash.
The SACU provides the mechanism needed to implement secure bus transactions to the system address
space.
The programming model for the system bus arbitration resides in the SCM. The SCM sources the
necessary control signals to the arbiter for bus master management.
The CWT provides a means of preventing system lockup due to uncontrolled software loops via a special
software service sequence. If periodic software servicing action does not occur, the CWT times out with a
programmed response (system reset or interrupt) to allow recovery or corrective action to be taken.
12.3 Features
The SCM includes these distinctive features:
• IPS base address register (IPSBAR)
— Base address location for 1-Gbyte peripheral space
— User control bits
• Processor-local memory base address register (RAMBAR)
• System control registers
— Core reset status register (CRSR) indicates type of last reset
— Core watchdog service register (CWSR) services watchdog timer
— Core watchdog control register (CWCR) for watchdog timer control
• System bus master arbitration programming model (MPARK)