Freescale Semiconductor ColdFire MCF52210 - Manual (Page 450)

Analog-to-Digital Converter (ADC)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
26-14 Freescale Semiconductor
26.4.8 Zero Crossing Status Register (ADZCSTAT)
The ADC zero crossing status (ADZCSTAT) register latches in the result of a sign comparison between
the current and previous sample. The type of comparison is controlled by the ADZCC register (see
Section 26.4.3, “Zero Crossing Control Register (ADZCC) ”).
For example, if the result for the channel programmed in SAMPLE0 changes sign from the previous
conversion, and the respective ZCE bit in the ADZCC register is set to 0b11 (any edge change), then the
ZCS0 bit is set. An interrupt is generated if CTRL1[ZCIE] is set.
These bits are sticky—they are not cleared automatically by subsequent conversions. A bit may only be
cleared by writing a 1 to it.
26.4.9 Result Registers (ADRSLTn)
The 8 result registers contain the converted results from a scan. The SAMPLEn result is loaded into
ADRSLTn. In a simultaneous parallel scan mode, the first channel pair, designated by SAMPLE0 and
SAMPLE4 in register LIST1/2, is stored in ADRSLT0 and ADRSLT4, respectively.
When writing to this register, only the RSLT portion of the value written is used. This value is modified as
shown in
Figure 26-23 and the result of the subtraction is stored. The SEXT bit is only set as a result of
this subtraction and is not directly determined by the value written.
RSLT can be interpreted as a signed integer or a signed fixed point (fractional) number. As a fixed point
number, RSLT can be used directly. If RSLT is interpreted as a signed integer, you have two options:
• Right shift with sign extend (ASR) three places to fit it into the range [0,4095]
• Accept the number as presented in the register, knowing there are missing codes, because the lower
three LSBs are always zero
IPSBAR
Offset: 0x19_0010 (ADZCSTAT)
Access: read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
ZCS7 ZCS6 ZCS5 ZCS4 ZCS3 ZCS2 ZCS1 ZCS0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-11. Zero Crossing Status Register (ADZCSTAT)
Table 26-13. ADLSTAT Field Descriptions
Field Description
15–8 Reserved, should be cleared.
7–0
ZCSn
Zero Crossing Status bits. These bits hold the result of a sign comparison between the current and previous
sample. The type of comparison is controlled by the ADZCC register (see
Section 26.4.3, “Zero Crossing
Control Register (ADZCC) ”).
0 Sample did not change sign, or sign comparison is disabled
1 Sample changed sign
Note: These bits are sticky, and can only be cleared by writing a 1 to them.