Freescale Semiconductor ColdFire MCF52210 - Manual (Page 498)

Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
28-2 Freescale Semiconductor
The first version 2 ColdFire core devices implemented the original debug architecture, now called revision
A. Based on feedback from customers and third-party developers, enhancements have been added to
succeeding generations of ColdFire cores. For revision A, CSR[HRL] is 0. See
Section 28.4.2,
“Configuration/Status Register (CSR)” .
Revision B (and B+) of the debug architecture offers more flexibility for configuring the hardware
breakpoint trigger registers and removing the restrictions involving concurrent BDM processing while
hardware breakpoint registers are active. Revision B+ adds three new PC breakpoint registers. For
revision B, CSR[HRL] is 1, and for revision B+, CSR[HRL] is 0x9.
The following table summarizes the various debug revisions.
28.2 Signal Descriptions
Table 28-2 describes debug module signals. All ColdFire debug signals are unidirectional and related to a
rising edge of the processor core’s clock signal. The standard 26-pin debug connector is shown in
Section 28.8, “Freescale-Recommended BDM Pinout” .
Table 28-1. Debug Revision Summary
Revision CSR[HRL] Enhancements
A 0000 Initial debug revision
B 0001 BDM command execution does not affect hardware breakpoint logic
Added BDM address attribute register (BAAR)
BKPT configurable interrupt (CSR[BKD])
Level 1 and level 2 triggers on OR condition, in addition to AND
SYNC _ PC command to display the processor’s current PC
B+ 1001 3 new PC breakpoint registers PBR1–3
Table 28-2. Debug Module Signals
Signal Description
Development Serial
Clock (DSCLK) Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication port to the debug module
during packet transfers. Maximum frequency is 1/5 the processor status clock (PSTCLK). At the
synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.
Development Serial
Input (DSI)
Internally synchronized input that provides data input for the serial communication port to the debug
module after the DSCLK has been seen as high (logic 1).
Development Serial
Output (DSO)
Provides serial output communication for debug module responses. DSO is registered internally. The
output is delayed from the validation of DSCLK high.
Breakpoint (BKPT) Input requests a manual breakpoint. Assertion of BKPT puts the processor into a halted state after
the current instruction completes. Halt status is reflected on processor status signals (PST[3:0]) as
the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a
debug interrupt exception in the processor.