Freescale Semiconductor ColdFire MCF52210 - Manual (Page 534)

Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
28-38 Freescale Semiconductor
28.5.3.3.13 Read Debug Module Register ( RDMREG )
Read the selected debug module register and return the 32-bit result. The only valid register selection for
the RDMREG command is CSR (DRc = 0x00). This read of the CSR clears CSR (FOF, TRG, HALT, and
BKPT) as well as the trigger status bits (CSR[BSTAT]) if a level-2 breakpoint is triggered or a level-1
breakpoint is triggered and no level-2 breakpoint has been enabled.
Command/Result Formats:
Table 28-23 shows the definition of DRc encoding.
Command Sequence:
Figure 28-41. RDMREG Command Sequence
Operand Data: None
Result Data: The contents of the selected debug register are returned as a longword value. The
data is returned most-significant word first.
28.5.3.3.14 Write Debug Module Register ( WDMREG )
The operand (longword) data is written to the specified debug module register. All 32 bits of the register
are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU
accesses are performed using the WDEBUG instruction.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Command 0x2 0xD 100 DRc
Result D[31:16]
D[15:0]
Figure 28-40. RDMREG Command/Result Formats
Table 28-23. Definition of DRc Encoding—Read
DRc[4:0] Debug Register Definition Mnemonic Initial State Page
0x00 Configuration/Status CSR 0x0090_0000 p. 28-7
0x01–0x1F Reserved — — —
RDMREG
???
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’