Freescale Semiconductor ColdFire MCF52210 - Manual (Page 141)

Power Management
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 8-13
8.4.2.6 I
2
C Module
When the I
2
C Module is enabled by the setting of the I2CR[IEN] bit and when the device is not in stop
mode, the I
2
C module is operable and may generate an interrupt to bring the device out of a low-power
mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the
I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller. The setting of I2SR[IIF]
signifies the completion of one byte transfer or the reception of a calling address matching its own
specified address when in slave receive mode.
In stop mode, the I
2
C Module stops immediately and freezes operation, register values, and external pins.
Upon exiting stop mode, the I
2
C resumes operation unless stop mode was exited by reset.
8.4.2.7 Queued Serial Peripheral Interface (QSPI)
In wait and doze modes, the queued serial peripheral interface (QSPI) may generate an interrupt to exit the
low-power modes.
• Clearing the QSPI enable bit (SPE) disables the QSPI function.
• The QSPI is unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the QSPI stops immediately and freezes operation, register values, state machines, and
external pins. During this mode, the QSPI clocks are shut down. Coming out of stop mode returns the QSPI
to operation from the state prior to the low-power mode entry.
8.4.2.8 DMA Timers (DTIM0–DTIM3)
In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode. This
interrupt can be generated when the DMA Timer is in input capture mode or reference compare mode.
In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has a
non-zero value and the DMA enable (DMAEN) bit of the DMA timer extended mode register (DTXMR)
is cleared, an interrupt is issued upon a captured input. In reference compare mode, where the output
reference request interrupt enable (ORRI) bit of DTMR is set and the DTXMR[DMAEN] bit is cleared,
an interrupt is issued when the timer counter reaches the reference value.
DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by the wait or doze modes
and may generate an interrupt to exit these modes. Upon exiting stop mode, the timer resumes operation
unless stop mode was exited by reset.
8.4.2.9 Interrupt Controllers (INTC0, INTC1)
The interrupt controller is not affected by any of the low-power modes. All logic between the input sources
and generating the interrupt to the processor is combinational to allow the ability to wake up the CPU
processor during low-power stop mode when all system clocks are stopped.
An interrupt request causes the CPU to exit a low-power mode only if that interrupt’s priority level is at or
above the level programmed in the interrupt priority mask field of the CPU’s status register (SR). The
interrupt must also be enabled in the interrupt controller’s interrupt mask register as well as at the module
from which the interrupt request would originate.