Freescale Semiconductor ColdFire MCF52210 - Manual (Page 277)

DMA Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-3
17.2 DMA Transfer Overview
The DMA module can data within system memory (including memory and peripheral devices) with
minimal processor intervention, greatly improving overall system performance. The DMA module
consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply
to any of the channels. It is not possible to implicitly address all four channels at once.
The processor generates DMA requests internally by setting DCR[START]; the UART modules and DMA
timers can generate a DMA request by asserting internal DREQ signals. The processor can program bus
bandwidth for each channel. The channels support cycle-steal and continuous transfer modes; see
Section 17.4.1, “Transfer Requests (Cycle-Steal and Continuous Modes) .”
The DMA controller supports dual-address transfers. The DMA channels support up to 32 data bits.
• Dual-address transfers—A dual-address transfer consists of a read followed by a write and is
initiated by an internal request using the START bit or by a peripheral DMA request. Two types of
transfer can occur: a read from a source device or a write to a destination device. See
Figure 17-2
for more information.
Figure 17-2. Dual-Address Transfer
Any operation involving the DMA module follows the same three steps:
1. Channel initialization—Channel registers are loaded with control information, address pointers,
and a byte-transfer count.
2. Data transfer—The DMA accepts requests for operand transfers and provides addressing and bus
control for the transfers.
3. Channel termination—Occurs after the operation is finished, successfully or due to an error. The
channel indicates the operation status in the channel’s DSR, described in Section 17.3.4, “Byte
Count Registers (BCRn) and DMA Status Registers (DSRn) .”
17.3 Memory Map/Register Definition
This section describes each internal register and its bit assignment. Modifying DMA control registers
during a DMA transfer can result in undefined operation.
Table 17-1 shows the mapping of DMA
controller registers.
DMA DMA
Memory/
Peripheral
Memory/
Peripheral
Control and Data
Control and Data