Freescale Semiconductor ColdFire MCF52210 - Manual (Page 281)

DMA Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-7
IPSBAR
Offsets: See Figure 17-6 (DSRn)
Access: read/write
7 6 5 4 3 2 1 0
R 0
CE BES BED
0
REQ BSY DONE
W
Reset: 0 0 0 0 0 0 0 0
Figure 17-7. DMA Status Registers (DSRn)
Table 17-3. DSRn Field Descriptions
Field Description
7 Reserved, should be cleared.
6
CE
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if
BCR equals 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to
DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
5
BES
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
4
BED
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
3 Reserved, should be cleared.
2
REQ
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
1
BSY
Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
0
DONE
Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error
conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also
be used to abort a transfer by resetting the status bits. When a transfer completes, software must clear DONE
before reprogramming the DMA.
0 Writing or reading a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used in an interrupt
handler to clear the DMA interrupt and error bits.