2 reset configuration register (rcon), 3 chip identification register (cir) – Freescale Semiconductor ColdFire MCF52210 User Manual
Page 148
Chip Configuration Module (CCM)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
9-4
Freescale Semiconductor
9.3.3.2
Reset Configuration Register (RCON)
At reset, RCON determines the default operation of certain chip functions. All default functions defined
by the RCON values can only be overridden during reset configuration if the external RCON pin is
asserted. RCON is a read-only register.
9.3.3.3
Chip Identification Register (CIR)
IPSBAR
Offset:
0x11_0008 (RCON)
Access: Supervisor read-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
RLOAD
0
0
0
0
MODE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-2. Reset Configuration Register (RCON)
Table 9-5. RCON Field Descriptions
Field
Description
15–6
Reserved, should be cleared.
5
RLOAD
Pad Driver Load. This read-only field reflects the reset value of the pin drive strength register. If booting into EzPort
mode, all pins default to high drive strength. In single-chip mode, all PDSR controlled pins default to low drive
strength,
0 Single-chip mode. All PDSR bits reset to 0 (low drive strength).
1 EzPort mode. All PDSR bits reset to 1 (high drive strength).
4–1
Reserved, should be cleared.
0
MODE
Chip Configuration Mode. Reflects the default chip configuration mode.
0 Single-chip mode (This is the value used for the MCF52211.)
1 Reserved.
The default mode cannot be overridden during reset configuration.
IPSBAR
Offset:
0x11_000A (CIR)
Access: read-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PIN
PRN
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
The reset value is device-dependent.
Figure 9-3. Chip Identification Register (CIR)