Freescale Semiconductor ColdFire MCF52210 - Manual (Page 414)

UART Modules
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
24-28 Freescale Semiconductor
To configure the UART for DMA requests:
1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the desired DMA
channels. For example, setting DMAREQC[7:4] to 1000 maps UART0 receive DMA requests to
DMA channel 1, setting DMAREQC[11:8] to 1101 maps UART1 transmit DMA requests to DMA
channel 2, and so on. It is possible to independently map transmit based and receive based UART
DMA requests in the DMAREQC.
2. Disable interrupts using the UIMR register. The appropriate UIMR bits must be cleared so that
interrupt requests are disabled for those conditions for which a DMA request is desired. For
example, to generate transmit DMA requests from UART1, UIMR1[TXRDY] should be cleared.
This prevents TXRDY from generating an interrupt request while a transmit DMA request is
generated.
3. Configure the GPACR and appropriate PACR registers located in the SCM for DMA access to
IPSBAR space.
4. Initialize the DMA channel. The DMA should be configured for cycle steal mode and a source and
destination size of one byte. This causes a single byte to be transferred for each UART DMA
request.
Table 24-14 shows the DMA requests.
24.5.2 UART Module Initialization Sequence
The following shows the UART module initialization sequence.
1. UCRn:
a) Reset the receiver and transmitter.
b) Reset the mode pointer (MISC[2–0] = 0b001).
2. UIMRn: Enable the desired interrupt sources.
3. UACRn: Initialize the input enable control (IEC bit).
4. UCSRn: Select the receiver and transmitter clock. Use timer as source if required.
5. UMR1n:
a) If preferred, program operation of receiver ready-to-send (RXRTS bit).
a) Select receiver-ready or FIFO-full notification (RXRDY/FFULL bit).
b) Select character or block error mode (ERR bit).
c) Select parity mode and type (PM and PT bits).
d) Select number of bits per character (B/Cx bits).
6. UMR2n:
a) Select the mode of operation (CM bits).
Table 24-14. UART DMA Requests
Register Bit DMA Request
UISRn 1 Receive DMA request
UISRn 0 Transmit DMA request