Freescale Semiconductor ColdFire MCF52210 - Manual (Page 189)

System Control Module (SCM)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-13
• User operand write
Instruction fetch accesses are associated with the execute attribute.
It should be noted that while the bus does not implement the concept of reference type (code versus data)
and only supports the user/supervisor privilege level, the reference type attribute is supported by the
system bus. Accordingly, the access checking associated with privilege level and reference type is
performed in the IPS controller using the attributes associated with the reference from the system bus.
The SACU partitions the access control mechanisms into three distinct functions:
• Master privilege register (MPR)
— Allows each bus master to be assigned a privilege level:
– Disable the master’s user/supervisor attribute and force to user mode access
– Enable the master’s user/supervisor attribute
— The reset state provides supervisor privilege to the processor core (bus master 0).
— Input signals allow the non-core bus masters to have their user/supervisor attribute enabled at
reset. This is intended to support the concept of a trusted bus master, and also controls the
ability of a bus master to modify the register state of any of the SACU control registers; that is,
only trusted masters can modify the control registers.
• Peripheral access control registers (PACRs)
— Provide read/write access rights, supervisor/user privilege levels.
— Reset state provides supervisor-only read/write access to these modules.
— Nine 8-bit registers control access to 17 of the on-chip peripheral modules
• Grouped peripheral access control registers (GPACR0, GPACR1)
— Provide read/write/execute access rights, supervisor/user privilege levels.
— One single register (GPACR0) controls access to 14 of the on-chip peripheral modules.
— One register (GPACR1) controls access for IPS reads and writes to the flash module.
— Reset state provides supervisor-only read/write access to each of these peripheral spaces.
12.7.3 Memory Map/Register Definition
The memory map for the SACU program-visible registers within the system control module (SCM) is
shown in
Table 12-8 . The MPR, PACR, and GPACRs are 8 bits wide.
Table 12-8. SACU Register Memory Map
IPSBAR
Offset
[31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0]
0x020 MPR PPMRS PPMRC IPSBMT
0x024 PACR0 PACR1 PACR2 PACR3
0x028 PACR4 PACR5 PACR6 PACR7
0x02C PACR8 — — —
0x030 GPACR0 GPACR1 — —