Freescale Semiconductor ColdFire MCF52210 - Manual (Page 357)

General Purpose Timer Module (GPT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-19
The PA counter register (GPTPACNT) reflects the number of pulses from the divide-by-64 clock since the
last reset.
NOTE
The GPT prescaler generates the divide-by-64 clock. If the timer is not
active, there is no divide-by-64 clock.
Figure 21-22. Channel 3 Output Compare/Pulse Accumulator Logic
21.7.7 General-Purpose I/O Ports
An I/O pin used by the timer defaults to general-purpose I/O unless an internal function that uses that pin
is enabled.
The PORTTn pins can be configured for an input capture function or an output compare function. The
IOSn bits in the GPT IC/OC select register configure the PORTTn pins as input capture or output compare
pins.
The PORTTn data direction register controls the data direction of an input capture pin. External pin
conditions trigger input captures on input capture pins configured as inputs.
To configure a pin for input capture:
1. Clear the pin’s IOS bit in GPTIOS.
2. Clear the pin’s DDR bit in PORTTnDDR.
3. Write to GPTCTL2 to select the input edge to detect.
PORTTnDDR does not affect the data direction of an output compare pin. The output compare function
overrides the data direction register but does not affect the state of the data direction register.
To configure a pin for output compare:
1. Set the pin’s IOS bit in GPTIOS.
2. Write the output compare value to GPTCn.
3. Clear the pin’s DDR bit in PORTTnDDR.
4. Write to the OMn/OLn bits in GPTCTL1 to select the output action.
Table 21-23 shows how various timer settings affect pin functionality.
PAD
OM3
OL3
CHANNEL 3 OUTPUT COMPARE
PULSE
ACCUMULATOR
OC3M3