Freescale Semiconductor ColdFire MCF52210 - Manual (Page 285)

DMA Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-11
17.4 Functional Description
In the following discussion, the term DMA request implies that DCRn[START] or DCRn[EEXT] is set,
followed by assertion of an internal or external DMA request. The START bit is cleared when the channel
begins an internal access.
Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE,DSIZE] are
consistent with the source and destination addresses. If they are not consistent, the configuration error bit,
DSRn[CE], is set. If misalignment is detected, no transfer occurs, DSRn[CE] is set, and, depending on the
DCR configuration, an interrupt event is issued. If the auto-align bit, DCRn[AA], is set, error checking is
performed on the appropriate registers.
A read/write transfer reads bytes from the source address and writes them to the destination address. The
number of bytes is the larger of the sizes specified by DCRn[SSIZE] and DCRn[DSIZE]. See
17.3.5,
“DMA Control Registers (DCRn) .”
5–4
LINKCC
Link channel control. Allows DMA channels to have their transfers linked. The current DMA channel triggers a
DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits.
00 No channel-to-channel linking
01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR
decrements to zero.
10 Perform a link to channel LCH1 after each cycle-steal transfer
11 Perform a link to channel LCH1 after the BCR decrements to zero
If not in cycle steal mode (DCRn[CS]=0) and LINKCC equals 01 or 10, no link to LCH1 occurs.
If LINKCC equals 01, a link to LCH1 is created after each cycle-steal transfer performed by the current DMA
channel is completed. As the last cycle-steal is performed and the BCR reaches zero, then the link to LCH1 is
closed and a link to LCH2 is created.
If the LINKCC field is non-zero, the contents of the bandwidth control field (DCRn[BWC]) are ignored and
effectively forced to zero by the DMA hardware. This is done to prevent any non-zero bandwidth control settings
from allowing channel arbitration while any type of link is to be performed.
3-2
LCH1
Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the
same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is
set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
1-0
LCH2
Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the
same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is
set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
Table 17-4. DCRn Field Descriptions (continued)
Field Description