Freescale Semiconductor ColdFire MCF52210 - Manual (Page 57)

ColdFire Core
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-13
Figure 3-15. V2 OEP Pipeline Execution Templates
3.3.2 Instruction Set Architecture (ISA_A+)
The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes
based on extensive analysis of embedded application code. The ISA was optimized for code compiled
from high-level languages where the dominant operand size was the 32-bit integer declaration. This
approach minimized processor complexity and cost, while providing excellent performance for compiled
applications.
After the initial ColdFire compilers were created, developers noted there were certain ISA additions that
would enhance code density and overall performance. Additionally, as users implemented ColdFire-based
designs into a wide range of embedded systems, they found certain frequently-used instruction sequences
that could be improved by the creation of additional instructions.
The original ISA definition minimized support for instructions referencing byte- and word-sized operands.
Full support for the move byte and move word instructions was provided, but the only other opcodes
supporting these data types are clr (clear) and tst (test). A set of instruction enhancements has been
implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three
areas:
1. Enhanced support for byte and word-sized operands
2. Enhanced support for position-independent code
3. Miscellaneous instruction additions to address new functionality
Core clock
Register-to-Register
Core Bus
Embedded-Load
Core Bus
Register-to-Memory
op read
Core Bus op write
OEP.DSOC OC next
OEP.AGEX EX
OEP.DSOC DS OC next
OEP.AGEX EX AG
OEP.DSOC DSOC next
OEP.AGEX AGEX
(Store)