Freescale Semiconductor ColdFire MCF52210 - Manual (Page 24)

Overview
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
1-8 Freescale Semiconductor
– Power-on reset (POR)
– External
– Software
– Watchdog
– Loss of clock / loss of lock
– Low-voltage detection (LVD)
– JTAG
— Status flag indication of source of last reset
• Chip integration module (CIM)
— System configuration during reset
— Selects one of six clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
• General purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
1.2.1 V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction
buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and
instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched
instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline
stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX)
performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
core includes the multiply-accumulate (MAC) unit for improved signal processing capabilities. The MAC
implements a three-stage arithmetic pipeline, optimized for 16
×16 bit operations, with support for one
32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers, signed
fractional operands, and a complete set of instructions to process these data types. The MAC provides
support for execution of DSP operations within the context of a single processor at a minimal hardware
cost.
1.2.2 Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug
and emulator development tools. Through a standard debug interface, access to debug information and