14 gpt channel registers (gptcn), 15 pulse accumulator control register (gptpactl) – Freescale Semiconductor ColdFire MCF52210 User Manual
Page 351
General Purpose Timer Module (GPT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
21-13
Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag
register 2.
21.6.14 GPT Channel Registers (GPTCn)
21.6.15 Pulse Accumulator Control Register (GPTPACTL)
Table 21-16. GPTFLG2 Field Descriptions
Field
Description
7
TOF
Timer overflow flag. Set when the GPT counter rolls over from 0xFFFF to 0x0000. If the TOI bit in GPTSCR2 is also
set, TOF generates an interrupt request. This bit is read anytime, write anytime (writing 1 clears the flag, and writing
0 has no effect).
1 Timer overflow
0 No timer overflow
Note: When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the
GPT counter registers go from 0xFFFF to 0x0000. When TOF is set, it does not inhibit subsequent overflow events.
6–0
Reserved, should be cleared.
IPSBAR
Offsets:
0x1A_0010 (GPTC0)
0x1A_0012 (GPTC1)
0x1A_0014 (GPTC2)
0x1A_0016 (GPTC3)
Access: Supervisor
read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CCNT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-16. GPT Channel[0:3] Register (GPTCn)
Table 21-17. GPTCn Field Descriptions
Field
Description
15–0
CCNT
When a channel is configured for input capture (IOSn = 0), the GPT channel registers latch the value of the
free-running counter when a defined transition occurs on the corresponding input capture pin.
When a channel is configured for output compare (IOSn = 1), the GPT channel registers contain the output compare
value.
To ensure coherent reading of the GPT counter, such that a timer rollover does not occur between back-to-back 8-bit
reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime (for
the output compare channel); writing to the input capture channel has no effect.
IPSBAR
Offset: 0x1A_0018 (GPTPACTL)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
PAE
PAMOD
PEDGE
CLK
PAOVI
PAI
W
Reset:
0
0
0
0
0
0
0
0
Figure 21-17. Pulse Accumulator Control Register (GPTPACTL)