2 memory map and register definition, 1 memory map, Memory map and register definition -2 – Freescale Semiconductor ColdFire MCF52210 User Manual

Page 124: Memory map -2, 1 wait mode, 2 doze mode, 3 stop mode

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Backup Watchdog Timer (BWT) Module

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

7-2

Freescale Semiconductor

7.1.2.1

Wait Mode

The functionality of the BWT in Wait mode depends on the value of WCR[WAIT].

When WCR[WAIT]=1, the BWT stops when the device enters Wait mode. When the device leaves Wait
mode, the BWT resumes from the state it was in when it stopped.

When WCR[WAIT]=0, the BWT continues to operate normally when the device enters Wait mode.

7.1.2.2

Doze Mode

The functionality of the BWT in Doze mode depends on the value of WCR[DOZE].

When WCR[DOZE]=1, the BWT stops when the device enters Doze mode. When the device leaves Doze
mode, the BWT resumes from the state it was in when it stopped.

When WCR[DOZE]=0, the BWT continues to operate normally when the device enters Doze mode.

7.1.2.3

Stop Mode

The functionality of the BWT in Stop mode depends on the value of WCR[STOP].

When WCR[STOP]=1, the BWT stops when the device enters Stop mode. When the device leaves Stop
mode, the BWT resumes from the state it was in when it stopped.

When WCR[STOP]=0, the BWT continues to operate normally when the device enters Stop mode.

7.2

Memory Map and Register Definition

The backup watchdog timer programming model includes registers in the BWT and clock modules. The
registers used to configure the BWT are read-always/write once, and their contents are preserved during a
warm reset. Only a Power-On Reset resets these registers to their default values.

7.2.1

Memory Map

Table 7-1. BWT Memory Map

IPSBAR

Offset

1

1

Addresses not assigned to a register and undefined register bits are reserved for expansion.

Register

Width

(bits)

Access

Reset Value

Section/Page

0x14_0000

Backup Watchdog Timer Control Register (WCR)

8

R/W

2

2

WCR and WMR are read-always/write-once, and cannot be changed until the next Power-On Reset event.

0x02

7.2.2.1/7-3

0x14_0002

Backup Watchdog Timer Modulus Register (WMR)

16

R/W

2

0xFFFF

7.2.2.2/7-4

0x14_0004

Backup Watchdog Timer Count Register (WCNTR)

16

R

0xFFFF

7.2.2.3/7-4

0x14_0006

Backup Watchdog Timer Service Register (WSR)

16

R/W

0x00

7.2.2.4/7-5

0x12_0013

Clock Module Backup Watchdog Timer Control Register
(BWCR)

3

3

This read-always/write-once register is part of the Clock Module; see

Section 6.7.1.10, “Backup Watchdog Timer Control

Register (BWCR)

,” for a detailed description.

8

R/W

3

0x02

6.7.1.10/6-16

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