Freescale Semiconductor ColdFire MCF52210 - Manual (Page 226)

Interrupt Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
14-16 Freescale Semiconductor
14.3.8 Global Level m IACK Registers (GLmIACK)
In addition to the software IACK registers ( Section 14.3.7, “Software and Level m IACK Registers
(SWIACKn, LmIACKn)” ), there are global IACK registers, GLmIACK. (There is no global SWIACK
register.) On devices with multiple interrupt controllers, a read from one of the GLmIACK registers returns
the vector for the highest priority unmasked interrupt within a level for all interrupt controllers. Because
the MCF52211 has only one interrupt controller, the global registers effectively provide the same
information as the LmIACK registers.
14.4 Low-Power Wakeup Operation
The system control module (SCM) contains an 8-bit low-power interrupt control register (LPICR) used
explicitly for controlling the low-power stop mode. This register must explicitly be programmed by
software to enter low-power mode.
The interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to
exit from the low-power stop mode. This special mode of operation works as follows:
1. LPICR[6:4] is loaded with the specified mask level while the core is in stop mode. LPICR[7] must
be set to enable this mode of operation.
NOTE
The wakeup mask level taken from LPICR[6:4] is adjusted by hardware to
allow a level 7 IRQ to generate a wakeup. That is, the wakeup mask value
used by the interrupt controller must be in the range of 0–6.
Table 14-14. SWIACKn and LmIACKn Field Descriptions
Field Description
7–0
VECTOR
Vector number. A read from the SWIACK register returns the vector number associated with the highest level,
highest priority unmasked interrupt source. A read from one of the LmIACK registers returns the highest priority
unmasked interrupt source within the level.
IPSBAR
Offsets:
See Table 14-2 for register offsets
(GLmIACK)
Access: read-only
7 6 5 4 3 2 1 0
R VECTOR
W
Reset: 0 0 0 0 0 0 0 0
Figure 14-11. Global Level m IACK Registers (GLmIACK)
Table 14-15. GSWIACK and GLnIACK Field Descriptions
Field Description
7–0
VECTOR
Vector number. A read from one of the LnIACK registers returns the vector for the highest priority unmasked interrupt
within a level for all interrupt controllers.
As implemented on the MCF52211, these registers contain the same information as LnIACK.