4 memory map/register definition, 4 memory map/register definition -6 – Freescale Semiconductor ColdFire MCF52210 User Manual

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Debug Module

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

28-6

Freescale Semiconductor

28.4

Memory Map/Register Definition

In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contain a number of registers to support the required functionality. These
registers are also accessible from the processor’s supervisor programming model by executing the
WDEBUG instruction (write only). Therefore, the breakpoint hardware in debug module can be read or
written by the external development system using the debug serial interface

or written by the operating

system running on the processor core. Software guarantees that accesses to these resources are serialized
and logically consistent. Hardware provides a locking mechanism in CSR to allow external development
system to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]).
BDM commands must not be issued if the ColdFire processor is using the WDEBUG instruction to access
debug module registers, or the resulting behavior is undefined. The DSCLK must be quiescent during
operation of the WDEBUG command.

These registers, shown in

Table 28-4

, are treated as 32-bit quantities, regardless of the number of

implemented bits. These registers are also accessed through the BDM port by the commands,

WDMREG

and

RDMREG

, described in

Section 28.5.3.3, “Command Set Descriptions”.

These commands contain a

5-bit field, DRc, that specifies the register, as shown in

Table 28-4