Freescale Semiconductor ColdFire MCF52210 - Manual (Page 511)

Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 28-15
28.4.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)
The PBRn registers define an instruction address for use as part of the trigger. These registers’ contents
are compared with the processor’s program counter register when the appropriate valid bit is set (for
PBR1–3) and TDR is configured appropriately. PBR0 bits are masked by setting corresponding PBMR
bits (PBMR has no effect on PBR1–3). Results are compared with the processor’s program counter
register, as defined in TDR. Breakpoint registers, PBR1–3, have no masking associated with them. The
12–6
L1ED
Enable Level 1 Data Breakpoint. Setting an L1ED bit enables the corresponding data breakpoint condition based on
the size and placement on the processor’s local data bus. Clearing all L1ED bits disables data breakpoints.
5
L1DI
Level 1 Data Breakpoint Invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a
trigger based on the occurrence of a data value other than the DBR contents.
0 No inversion
1 Invert data breakpoint comparators.
4–2
L1EA
Enable Level 1 Address Breakpoint. Setting an L1EA bit enables the corresponding address breakpoint. Clearing all
three bits disables the address breakpoint.
1
L1EPC
Enable Level 1 PC breakpoint.
0 Disable PC breakpoint
1 Enable PC breakpoint
0
L1PCI
Level 1 PC Breakpoint Invert.
0 The PC breakpoint is defined within the region defined by PBRn and PBMR.
1 The PC breakpoint is defined outside the region defined by PBRn and PBMR.
Table 28-9. TDR Field Descriptions (continued)
Field Description
TDR Bit Description
12 Data longword. Entire processor’s local data bus.
11 Lower data word.
10 Upper data word.
9 Lower lower data byte. Low-order byte of the low-order word.
8 Lower middle data byte. High-order byte of the low-order word.
7 Upper middle data byte. Low-order byte of the high-order word.
6 Upper upper data byte. High-order byte of the high-order word.
TDR Bit Description
4 Enable address breakpoint inverted. Breakpoint is based
outside the range between ABLR and ABHR.
3 Enable address breakpoint range. The breakpoint is based on
the inclusive range defined by ABLR and ABHR.
2 Enable address breakpoint low. The breakpoint is based on the
address in the ABLR.