Freescale Semiconductor ColdFire MCF52210 - Manual (Page 140)

Power Management
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
8-12 Freescale Semiconductor
further details). A peripheral may be disabled at any time and remains disabled during any low-power
mode of operation.
8.4.2 Peripheral Behavior in Low-Power Modes
8.4.2.1 ColdFire Core
The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any
low-power mode.
8.4.2.2 Static Random-Access Memory (SRAM)
SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power
mode.
8.4.2.3 System Control Module (SCM)
The SCM’s core watchdog timer can bring the device out of all low-power modes except stop mode. In
stop mode, all clocks stop, and the core watchdog does not operate.
When enabled, the core watchdog can bring the device out of low-power mode via a core watchdog
interrupt. This system setup must meet the conditions specified in
Section 8.4.1, “Low-Power Modes ” for
the core watchdog interrupt to bring the part out of low-power mode.
8.4.2.4 DMA Controller (DMA0–DMA3)
In wait and doze modes, the DMA controller is capable of bringing the device out of a low-power mode
by generating an interrupt upon completion of a transfer or an error condition. The completion of transfer
interrupt is generated when DMA interrupts are enabled by the setting of the DCR[INT] bit, and an
interrupt is generated when the DSR[DONE] bit is set. The interrupt upon error condition is generated
when the DCR[INT] bit is set, and an interrupt is generated when the CE, BES, or BED bit in the DSR
becomes set.
The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode.
8.4.2.5 UART Modules (UART0, UART1, and UART2)
In wait and doze modes, the UART may generate an interrupt to exit the low-power modes.
• Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART functions.
• The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and
external pins. During this mode, the UART clocks are shut down. Coming out of stop mode returns the
UARTs to operation from the state prior to the low-power mode entry.