Freescale Semiconductor ColdFire MCF52210 - Manual (Page 80)

Multiply-Accumulate Unit (MAC)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
4-4 Freescale Semiconductor
Table 4-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
4.2.2 Mask Register (MASK)
The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved
with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source
operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.
This register performs a simple AND with the operand address for MAC instructions. That is, the
processor calculates the normal operand address and, if enabled, that address is then ANDed with
{0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand
address can be constrained to a certain memory region. This is used primarily to implement circular queues
with the (An)+ addressing mode.
This minimizes the addressing support required for filtering, convolution, or any routine that implements
a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be
included in all memory effective address calculations. The syntax is as follows:
mac.sz Ry,RxSF,<ea>y&,Rw
The & operator enables the MASK use and causes bit 5 of the extension word to be set. The exact
algorithm for the use of MASK is:
1
V
Overflow. Set if an arithmetic overflow occurs, implying that the result cannot be represented in the operand
size. After set, V remains set until the accumulator register is loaded with a new value or MACSR is directly
loaded. MULS and MULU instructions do not change this value.
0 Carry. This field is always zero.
Table 4-3. Summary of S/U, F/I, and R/T Control Bits
S/U F/I R/T Operational Modes
0 0 x Signed, integer
0 1 0 Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
0 1 1 Signed, fractional
Round on MAC.L and MSAC.L
No round on accumulator stores
1 0 x Unsigned, integer
1 1 0 Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
1 1 1 Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Table 4-2. MACSR Field Descriptions (continued)
Field Description