3 pit count register (pcntrn), 3 functional description, 1 set-and-forget timer operation – Freescale Semiconductor ColdFire MCF52210 User Manual
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Programmable Interrupt Timers (PIT0–PIT1)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
20-5
20.2.3
PIT Count Register (PCNTRn)
The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two 8-bit reads
is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally.
20.3
Functional Description
This section describes the PIT functional operation.
20.3.1
Set-and-Forget Timer Operation
This mode of operation is selected when the RLD bit in the PCSR register is set.
When PIT counter reaches a count of 0x0000, PIF flag is set in PCSRn. The value in the modulus register
loads into the counter, and the counter begins decrementing toward 0x0000. If the PCSRn[PIE] bit is set,
the PIF flag issues an interrupt request to the CPU.
When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without
having to wait for the count to reach 0x0000.
Table 20-4. PMRn Field Descriptions
Field
Description
15–0
PM
Timer modulus. The value of this register is loaded into the PIT counter when the count reaches zero and the
PCSRn[RLD] bit is set. However, if PCSRn[OVW] is set, the value written to this field is immediately loaded into the
counter. Reading this field returns the value written.
IPSBAR
Offset:
0x15_0004 (PCNTR0)
0x16_0004 (PCNTR1)
Access: User read only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PC
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 20-4. PIT Count Register (PCNTRn)
Table 20-5. PCNTRn Field Descriptions
Field
Description
15–0
PC
Counter value. Reading this field with two 8-bit reads is not guaranteed coherent. Writing to PCNTRn has no effect,
and write cycles are terminated normally.