Freescale Semiconductor ColdFire MCF52210 - Manual (Page 576)

Revision History
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
B-2 Freescale Semiconductor
B.2 Changes between Rev. 0 and Rev. 1
Table 2. MCF52211RM Rev. 0 to Rev. 1 Changes
Location Description
Throughout • Formatting, layout, spelling, and grammar corrections.
• Removed the “Preliminary” label.
Table 2-1 / Page 2-3 Synchronized the table in the reference manual and the device data sheet.
Table 6-4 / Page 6-6 Corrected the CCHR reset value (was 0x04, is 0x05).
Figure 6-12 / Page 6-19 Deleted the RS resistor.
Chapter 8 Deleted references to nonexistent FlexCAN module.
Chapter 11 Added information about the RTC general oscillator count registers, RTCGOCU and RTCGOCL.
Figure 11-13 Corrected the code example for initializing the RTC.
Section 12.5.4 / Page 12-7 Updated the section to reflect the fact that the CWT does not cause a hardware reset.
Table 12-6 / Page 12-8 In the CWCR[CWRI] field description, changed “The interrupt level for the CWT is programmed
in the interrupt control register 7 (ICR7)...” to “The interrupt level for the CWT is programmed in
the interrupt control register 8 (ICR8)...”.
Section 12.7.3.1 / Page 12-14 • Rewrote the introductory text describing the MPR (removing erroneous reference to a fast
Ethernet controller).
• Corrected the MPR reset value (was 0x11, is 0x1).
Table 12-15 / Page 12-18 Deleted reference to nonexistent FlexCAN module.
Section 14-1 / Page 14-2 Deleted the sentence beginning with “For many peripheral devices...”.
Table 14-2 / Page 14-5 Deleted the entry for the (nonexistent) GSWIACK register.
Section 14.3.8 / Page 14-16 Deleted references to the (nonexistent) GSWIACK register.
Table 15-4 / Page 15-10 Corrected the acronym for the SOF threshold register (was OSOF_THLDL, is SOF_THLD).
Table 15-35 / Page 15-31 Corrected the descriptions of USB_CTRL[PDE] (when this bit is cleared, weak pulldowns are
disabled; when this bit is set, weak pulldowns are enabled).
Section 17.4 / Page 17-12 Deleted the sentence “BCRn decrements when an address transfer write completes for a
single-address access (DCRn[SAA] = 0), or when SAA equals 1.”
Figure 24-6 / Page 24-9 Added a note to clarify the UCSRn reset values.
Figure 24-20 / Page 24-21 • Corrected the label of the top signal (was UnTXD, is UnRXD).
• Corrected the text in the footnote (was TXRTS, is RXRTS).
Figure 24-23 / Page 24-24 Corrected the UnTXD label (was “Input”, is “Output”).
Figure 24-24 / Page 24-25 • Corrected a label on the bottom row (was UMR1n[PT]=2, is UMR1n[PT]=1).
• Deleted duplicate UMR1n[PM]=11 label.
Section 24.5.1.2 / Page 24-27 Added example DMA configuration steps.
Section 27.3.2.5.1 / Page
27-18
Corrected the numerical values in the left-aligned example.
Section 27.3.2.6.1 / Page
27-20
Corrected the numerical values in the center-aligned example.
Appendix A • Corrected the acronym for the SOF threshold register (was OSOF_THLDL, is SOF_THLD).
• Deleted the entry for the (nonexistent) GSWIACK register.
• Added entries for the RTCGOCU and RTCGOCL registers.