Freescale Semiconductor ColdFire MCF52210 - Manual (Page 365)

DMA Timers (DTIM0–DTIM3)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-5
22.2.3 DMA Timer Event Registers (DTERn)
DTERn, shown in Figure 22-4 , reports capture or reference events by setting DTERn[CAP] or
DTERn[REF]. This reporting happens regardless of the corresponding DMA request or interrupt enable
values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].
Writing a 1 to DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value); both bits can
be cleared at the same time. If configured to generate an interrupt request, REF and CAP bits should be
cleared early in the interrupt service routine so the timer module can negate the interrupt request signal to
the interrupt controller. If configured to generate a DMA request, processing of the DMA data transfer
automatically clears the REF and CAP flags via the internal DMA ACK signal.
Table 22-3. DTXMRn Field Descriptions
Field Description
7
DMAEN
DMA request. Enables DMA request output on counter reference match or capture edge event.
0 DMA request disabled
1 DMA request enabled
6
HALTED
Controls the counter when the core is halted. This allows debug mode to be entered without timer interrupts affecting
the debug flow.
0 Timer function is not affected by core halt.
1 Timer stops counting while the core is halted.
Note: This bit is only applicable in reference compare mode, see
Section 22.3.3, “Reference Compare.”
5–1 Reserved, must be cleared.
0
MODE16
Selects the increment mode for the timer. Setting MODE16 is intended to exercise the upper bits of the 32-bit timer
in diagnostic software without requiring the timer to count through its entire dynamic range. When set, the counter’s
upper 16 bits mirror its lower 16 bits. All 32 bits of the counter remain compared to the reference value.
0 Increment timer by 1
1 Increment timer by 65,537
IPSBAR
Offset:
0x00_0403 (DTER0)
0x00_0443 (DTER1)
0x00_0483 (DTER2)
0x00_04C3 (DTER3) Access: User read/write
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 REF CAP
W w1c w1c
Reset: 0 0 0 0 0 0 0 0
Figure 22-4. DTERn Registers