Freescale Semiconductor ColdFire MCF52210 - Manual (Page 286)

DMA Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
17-12 Freescale Semiconductor
Source and destination address registers (SARn and DARn) can be programmed in the DCRn to increment
at the completion of a successful transfer.
17.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)
The DMA channel supports internal and external requests. A request is issued by setting DCRn[START]
or when a UART or DMA timer asserts a DMA request. Setting DCRn[EEXT] enables recognition of
external DMA requests. Selecting between cycle-steal and continuous modes minimizes bus usage for
internal or external requests.
• Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination occurs
for each request. If DCRn[EEXT] is set, a request can be internal or external. An internal request
is selected by setting DCRn[START]. An external request is initiated by an on-chip peripheral
while DCRn[EEXT] is set.
• Continuous mode (DCRn[CS] = 0)—After an internal or external request, the DMA continuously
transfers data until BCRn reaches zero or a multiple of DCRn[BWC] or until DSRn[DONE] is set.
If BCRn is a multiple of BWC, the DMA request signal is negated until the bus cycle terminates
to allow the internal arbiter to switch masters. DCRn[BWC] equaling 000 specifies the maximum
transfer rate; other values specify a transfer rate limit.
The DMA performs the specified number of transfers, then relinquishes bus control. The DMA
negates its internal bus request on the last transfer before BCRn reaches a multiple of the boundary
specified in BWC. Upon completion, the DMA reasserts its bus request to regain mastership at the
earliest opportunity. The DMA loses bus control for a minimum of one bus cycle.
17.4.2 Dual-Address Data Transfer Mode
Each channel supports dual-address transfers. Dual-address transfers consist of a source data read and a
destination data write. The DMA controller module begins a dual-address transfer sequence during a DMA
request. If no error condition exists, DSRn[REQ] is set.
• Dual-address read—The DMA controller drives the SARn value onto the internal address bus. If
DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon a successful
read cycle. When the appropriate number of read cycles complete (multiple reads if the destination
size is larger than the source), the DMA initiates the write portion of the transfer.
If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop.
• Dual-address write—The DMA controller drives the DARn value onto the address bus. If
DCRn[DINC] is set, DARn increments by the appropriate number of bytes at the completion of a
successful write cycle. BCRn decrements by the appropriate number of bytes. DSRn[DONE] is set
when BCRn reaches zero. If the BCRn is greater than zero, another read/write transfer is initiated.
If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of
the bus cycle to allow the internal arbiter to switch masters.
If a termination error occurs, DSRn[BED,DONE] are set and DMA transactions stop.