Freescale Semiconductor ColdFire MCF52210 - Manual (Page 451)

Analog-to-Digital Converter (ADC)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 26-15
Negative results (SEXT = 1) are always presented in twos-complement format. If an application requires
that the result be always positive, the corresponding offset register (ADOFSn) must be set to 0x0.
The interpretation of the numbers programmed into the ADC limit and offset registers (ADLLMTn,
ADHLMTn, and ADOFSn) must match your interpretation of the result register.
26.4.10 Low and High Limit Registers (ADLLMTn and ADHLMTn)
Each ADC sample is compared against the values in the limit registers. The comparison is based upon the
raw conversion value before the offset correction is applied. Refer to
Figure 26-23 . ADC limit registers
(ADLLMTn and ADHLMTn) correspond to result registers (ADRSLTn). The high limit register is used
for the comparison of result > high limit. The low limit register is used for the comparison of result < low
limit.
Limit checking can be disabled by programming the respective limit register with 0x7FF8 for the high
limit and 0x0000 for the low limit. At reset, limit checking is disabled.
IPSBAR
Offsets:
0x19_0012 (ADRSLT0)
0x19_0014 (ADRSLT1)
0x19_0016 (ADRSLT2)
0x19_0018 (ADRSLT3)
0x19_001A (ADRSLT4)
0x19_001C (ADRSLT5)
0x19_001E (ADRSLT6)
0x19_0020 (ADRSLT7) Access: read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SEXT
RSLT
0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-12. Result Registers (ADRSLTn)
Table 26-14. ADRSLTn Field Descriptions
Field Description
15
SEXT
Sign Extend bit.
0 Result is positive
1 Result is negative
Note: If only positive results are required, then the respective offset register (ADOFSn) must be set to 0x0.
14–3
RSLT
Result of the conversion.
2–0 Reserved, should be cleared.