Freescale Semiconductor ColdFire MCF52210 - Manual (Page 29)

Overview
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-13
1.2.17 Backup Watchdog Timer
The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer,
facilitates recovery from runaway code. This timer is a free-running down-counter that generates a reset
on underflow. To prevent a reset, software must periodically restart the countdown. The backup watchdog
timer can be clocked by either the relaxation oscillator or the system clock.
1.2.18 Phase-Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked
loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control
logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own
power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins,
VDD and VSS.
1.2.19 Interrupt Controller (INTC)
The MCF52211 has a single interrupt controller that supports up to 63 interrupt sources. There are 56
programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining
seven sources are unassigned and may be used for software interrupt requests.
1.2.20 DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with
minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line
transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the
occurrence of certain UART or DMA timer events.
1.2.21 Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and
keeps track of what caused the last reset. There are seven sources of reset:
• External reset input
• Power-on reset (POR)
• Watchdog timer
• Phase locked-loop (PLL) loss of lock / loss of clock
• Software
• Low-voltage detector (LVD)
• JTAG
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other
registers provide status flags indicating the last source of reset and a control bit for software assertion of
the RSTO pin.