Hps triggering fpga example, Hps triggering fpga example -104 – Altera SoC Embedded Design Suite User Manual

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Quartus SignalTap II GUI has the above depicted Trigger panel that controls cross-triggering:
• The Trigger In panel determines whether HPS can trigger FPGA. Trigger In can be enabled and the

Pattern can be selected with Don't care, Low, High, Rising Edge, for instance.

• The Trigger out panel determines whether FPGA can trigger HPS. Trigger out can be enabled and the

Level can be selected: Active High and Active Low.
Note: Changing some of the settings requires recompiling the FPGA design. For this getting started

scenario, you will change only options that do not require recompilation.

The SignalTap II file that is provided with the Cyclone V GHRD has only the options that do not

require compilation enabled to be edited. If you recompile the design, you can enable all options to be

edited by selecting the Lock Mode to be Allow all changes.

Figure 4-85: SignalTap Lock Mode

HPS Triggering FPGA Example

This section presents an example on how stopping HPS execution in the debugger can trigger FPGA to

perform a SignalTap II acquisition. This can be useful, for example, if we want to see the state of some

FPGA signals at the time the HPS is stopped in the debugger.
The required steps are to reproduce this scenario:
1. Perform the steps from the Cross-triggering Prerequisites section.

2. Open the Debugger configuration and edit DTSL options to enable FPGA cross-triggering HPS as

shown in the Enabling Cross-triggering on HPS section.
a. Un-check the Enable FPGA -> HPS Cross Triggering check box.

b. Check the Enable HPS-> FPGA Cross Triggering check box if checked.

c. Check the Assume Cross Triggers can be accessed check box.

3. Start the debug session by clicking Debug in the Debug Configuration dialog box. The debugger will

stop the Linux kernel and display the current HPS state.

4. In Signal Tap II, make sure all trigger signals are disabled by setting their condition to Don't care.

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HPS Triggering FPGA Example

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2014.12.15

Altera Corporation

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