Altera SoC Embedded Design Suite - Manual (Page 125)

Figure 4-88: Run Analysis
8. SignalTap II will run the analysis and wait for the trigger from HPS:
Figure 4-89: Acquisition in Progress
9. In Eclipse debugger, click the Interrupt button or press F9. This will stop the cores and send the
trigger to FPGA.
10.SignalTap II will detect the trigger from HPS, perform an acquisition and stop. This will be indicated
by the status changing back to Ready to acquire.
Related Information
• ARM DS-5 Altera Edition on page 5-1
For more information, refer to the ARM DS-5 Altera Edition section.
• Cyclone V Coresight Debug and Trace
For more information about Tracing, refer to the Coresight Debug and Trace section in volume 3 of
the Cycone V Device Handbook.
• Online ARM DS-5 Documentation
The ARM DS-5 Altera Edition reference material can be accessed online on the documentation page of
the ARM website (www.arm.com); and from Eclipse by navigating to Help > Help Contents > ARM
DS-5 Documentation.
• Rocket Boards
For more information about Linux, refer to the Rocketboards website.
4-106 HPS Triggering FPGA Example
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2014.12.15
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