Intel 80C188XL - Manual (Page 113)

BUS INTERFACE UNIT
3-32
Figure 3-28. Returning to HALT After a DMA Bus Cycle
3.5.6 Exiting HALT
An NMI or any unmasked INTn interrupt causes the BIU to exit HALT. The first bus operations
to occur after exiting HALT are read cycles to reload the CS:IP registers. Figure 3-29 shows how
the HALT bus state is exited when an NMI or INTn occurs.
T1 T2 T3 T4 T1 T2 T3 TI
CLKOUT
AD15:0
[AD7:0]
TI TI
ALE
[A15:8]
A19:16
Valid Status Valid Status
Note Addr 8H 8H
Note Valid Valid
NOTE: Drives previous bus cycle value.
TI
BHE
[RFSH=1]
S2:0
T4
Address Note Address
Addr
Addr Valid Data Addr
A1515-0A