Intel 80C188XL - Manual (Page 148)

5-9
CLOCK GENERATION AND POWER MANAGEMENT
Figure 5-7. Warm Reset Waveform
At the second falling CLKOUT edge after sampling RES inactive, the processor deasserts RE-
SET. Bus activity starts 6½ CLKOUT periods after recognition of RES in the logic high state. If
an alternate bus master asserts HOLD during reset, the processor immediately asserts HLDA and
will not prefetch instructions.
A1522-0B
RES
AD15:0
S2:0, RD
WR, DEN
DT/R
LOCK
Minimum RES low
time 4 CLKOUT
periods.
UCS, LCS
MCS3:0
PCS6:0,NCS
TMR OUT0
TMR OUT1
X1
CLKOUT
A19/S6:
A16
RESET
HLDA, ALE
RES high
to first bus
activity 7
CLKOUT
periods.