Intel 80C188XL - Manual (Page 92)

3-11
BUS INTERFACE UNIT
Figure 3-10. Address/Status Phase Signal Relationships
ALE
AD15:0
A19:16
CLKOUT
S2:0
BHE
T4
or TI T1 T2
1
4
2
3
5
6
Valid
Valid
NOTES:
1. TCHLH TCHSV : Clock high to ALE high, S2:0 valid.
2. TCLAV : Clock low to address valid, BHE valid.
3. TAVLL : Address valid to ALE low (address setup to ALE).
4. TCHLL : Clock high to ALE low.
5. TCLAZ : Clock low to address invalid (address hold from clock low).
6. TLLAX : ALE low to address invalid (address hold from ALE).
Valid
Address
A1509-0A