Intel 80C188XL - Manual (Page 316)

A-9
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
A.2.2 Arithmetic Instructions
IMUL destination, source, data
IMUL (integer immediate multiply, signed) allows a value to be multiplied by an immediate op-
erand. IMUL requires three operands. The first, destination, is the register where the result will
be placed. The second, source, is the effective address of the multiplier. The source may be the
same register as the destination, another register or a memory location. The third, data, is an im-
mediate value used as the multiplicand. The data operand may be a byte or word. If data is a byte,
it is sign extended to 16 bits. Only the lower 16 bits of the result are saved. The result must be
placed in a general-purpose register.
A.2.3 Bit Manipulation Instructions
This section describes the eight enhanced bit-manipulation instructions.
A.2.3.1 Shift Instructions
SAL destination, count
SAL (immediate shift arithmetic left) shifts the destination operand left by an immediate value.
SAL has two operands. The first, destination, is the effective address to be shifted. The second,
count, is an immediate byte value representing the number of shifts to be made. The CPU will
AND count with 1FH before shifting, to allow no more than 32 shifts. Zeros shift in on the right.
SHL destination, count
SHL (immediate shift logical left) is physically the same instruction as SAL (immediate shift
arithmetic left).
SAR destination, count
SAR (immediate shift arithmetic right) shifts the destination operand right by an immediate val-
ue. SAL has two operands. The first, destination, is the effective address to be shifted. The sec-
ond, count, is an immediate byte value representing the number of shifts to be made. The CPU
will AND count with 1FH before shifting, to allow no more than 32 shifts. The value of the orig-
inal sign bit shifts into the most-significant bit to preserve the initial sign.
SHR destination, count
SHR (immediate shift logical right) is physically the same instruction as SAR (immediate shift
arithmetic right).