Intel 80C188XL - Manual (Page 147)

CLOCK GENERATION AND POWER MANAGEMENT
5-8
Figure 5-6. Cold Reset Waveform
RES
AD15:0, S2:0
RD, WR, DEN
DT/R, LOCK
Vcc cc
Vcc and X1 stable to RES high,
approximately 32 X1 periods.
UCS, LCS
MCS3:0, NCS
TMR OUT0
TMR OUT1
PCS6:0
NOTE: CLKOUT synchronization occurs 1 1/2 X1 periods after RES is sampled low.
X1
CLKOUT
A19:16
RESET
HLDA, ALE
RES high to
first bus activity,
7 CLKOUT periods.
V and X1 stable to output valid 28 X1 periods (max)
A1508-0B