Intel 80C188XL - Manual (Page 70)

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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2. The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. This
prevents maskable interrupts or single step exceptions from interrupting the processor
during the interrupt service routine.
3. The current CS and IP are pushed onto the stack.
4. The CPU fetches the new CS and IP for the interrupt vector routine from the Interrupt
Vector Table and begins executing from that point.
The CPU is now executing the interrupt service routine. The programmer must save (usually by
pushing onto the stack) all registers used in the interrupt service routine; otherwise, their contents
will be lost. To allow nesting of maskable interrupts, the programmer must set the Interrupt En-
able bit in the Processor Status Word.
When exiting an interrupt service routine, the programmer must restore (usually by popping off
the stack) the saved registers and execute an IRET instruction, which performs the following
steps.
1. Loads the return CS and IP by popping them off the stack.
2. Pops and restores the old Processor Status Word from the stack.
The CPU now executes from the point at which the interrupt or exception occurred.