Intel 80C188XL - Manual (Page 404)

Index-7
INDEX
SI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32,
2-34
Sign Flag (SF), 2-7, 2-9
Single-step trap (Type 1 exception), 2-43
Software
code example
80C187 floating-point routine, 10-16
80C187 initialization, 10-13–10-15
digital one-shot, 9-17–9-23
DMA initialization, 10-22–10-27
ICU initialization, 8-31
real-time clock, 9-17–9-19
square-wave generator, 9-17–9-22
TCU configurations, 9-17–9-23
timed DMA transfers, 10-22–10-27
data types, 2-37, 2-38
dynamic code relocation, 2-13, 2-14
interrupts, 2-45
overview, 2-17
See also Addressing modes, Instruction set
Square-wave generator, code example, 9-17–9-22
SRDY, See READY
SS register, 2-1, 2-5, 2-6, 2-13, 2-15, 2-30, 2-45
Stack frame pointers, A-2
Stack Pointer, 2-1, 2-5, 2-13, 2-15, 2-45
Stack segment, 2-5
Stacks, 2-15
START registers, CSU, 6-6, 6-7
STOP registers, CSU, 6-6, 6-8
String instructions, 2-22–2-23
and addressing modes, 2-34
and memory-mapped I/O ports, 2-36
operand locations, 2-13
operands, 2-36
Strings
accessing, 2-13, 2-34
defined, 2-37
Synchronizing asynchronous inputs, B-1
T
Technical support, 1-6
Temporary real, defined, 10-7
Terminology
"above" vs "greater", 2-26
"below" vs "less", 2-26
device names, 1-2
Timer Control Registers (TxCON), 9-7, 9-8
Timer Count Registers (TxCNT), 9-10
Timer Counter Unit (TCU), 9-1–9-23
application examples, 9-17–9-23
block diagram, 9-2
clock sources, 9-12
configuring a digital one-shot, 9-17–9-23
configuring a real-time clock, 9-17–9-19
configuring a square-wave generator, 9-17–
9-22
counting sequence, 9-12–9-13
dual maxcount mode, 9-13–9-14
enabling and disabling counters, 9-15–9-16
frequency, maximum, 9-17
initializing, 9-11
input synchronization, 9-17
interrupts, 9-16
overview, 9-1–9-6
programming, 9-6–9-16
considerations, 9-16
pulsed output, 9-14–9-15
retriggering, 9-13–9-14
setup and hold times, 9-16
single maxcount mode, 9-13, 9-14–9-16
timer delay, 9-1
timing, 9-1
and BIU, 9-1
considerations, 9-16
TxOUT signal, 9-15
variable duty cycle output, 9-14–9-15
Timer Maxcount Compare Registers (TxCMPA,
TxCMPB), 9-11
Timers‚ See Timer Counter Unit (TCU)
Training, 1-7
Trap exceptions, 2-43
Trap Flag (TF), 2-7, 2-9, 2-43, 2-48
T-state
and bus cycles, 3-9
and CLKOUT, 3-8
defined, 3-7
W
Wait states
and bus cycles, 3-13
and bus ready inputs, 3-13
and chip-selects, 6-15–6-17
and DRAM controllers, 7-1