Intel 80C188XL - Manual (Page 5)

CONTENTS
iv
2.3 INTERRUPTS AND EXCEPTION HANDLING ............................................................ 2-39
2.3.1 Interrupt/Exception Processing ...............................................................................2-39
2.3.1.1 Non-Maskable Interrupts ...............................................................................2-42
2.3.1.2 Maskable Interrupts .......................................................................................2-43
2.3.1.3 Exceptions .....................................................................................................2-43
2.3.2 Software Interrupts ..................................................................................................2-45
2.3.3 Interrupt Latency .....................................................................................................2-45
2.3.4 Interrupt Response Time ........................................................................................2-46
2.3.5 Interrupt and Exception Priority ...............................................................................2-46
CHAPTER 3
BUS INTERFACE UNIT
3.1 MULTIPLEXED ADDRESS AND DATA BUS ................................................................ 3-1
3.2 ADDRESS AND DATA BUS CONCEPTS ..................................................................... 3-1
3.2.1 16-Bit Data Bus .........................................................................................................3-1
3.2.2 8-Bit Data Bus ...........................................................................................................3-5
3.3 MEMORY AND I/O INTERFACES................................................................................. 3-6
3.3.1 16-Bit Bus Memory and I/O Requirements ...............................................................3-7
3.3.2 8-Bit Bus Memory and I/O Requirements .................................................................3-7
3.4 BUS CYCLE OPERATION ............................................................................................ 3-7
3.4.1 Address/Status Phase ............................................................................................3-10
3.4.2 Data Phase .............................................................................................................3-13
3.4.3 Wait States ..............................................................................................................3-13
3.4.4 Idle States ...............................................................................................................3-18
3.5 BUS CYCLES .............................................................................................................. 3-20
3.5.1 Read Bus Cycles ....................................................................................................3-20
3.5.1.1 Refresh Bus Cycles .......................................................................................3-22
3.5.2 Write Bus Cycles .....................................................................................................3-22
3.5.3 Interrupt Acknowledge Bus Cycle ...........................................................................3-25
3.5.3.1 System Design Considerations .....................................................................3-27
3.5.4 HALT Bus Cycle ......................................................................................................3-28
3.5.5 Temporarily Exiting the HALT Bus State .................................................................3-30
3.5.6 Exiting HALT ...........................................................................................................3-32
3.6 SYSTEM DESIGN ALTERNATIVES ........................................................................... 3-33
3.6.1 Buffering the Data Bus ............................................................................................3-34
3.6.2 Synchronizing Software and Hardware Events .......................................................3-36
3.6.3 Using a Locked Bus ................................................................................................3-37
3.6.4 Using the Queue Status Signals .............................................................................3-38
3.7 MULTI-MASTER BUS SYSTEM DESIGNS................................................................. 3-39
3.7.1 Entering Bus HOLD ................................................................................................3-39
3.7.1.1 HOLD Bus Latency ........................................................................................3-40
3.7.1.2 Refresh Operation During a Bus HOLD ........................................................3-41
3.7.2 Exiting HOLD ..........................................................................................................3-43
3.8 BUS CYCLE PRIORITIES ........................................................................................... 3-44