Figure 313. typical bus cycle with wait states, Figure 314. ardy and srdy pin block diagram, Tates. figure 3-13 – Intel 80C188XL User Manual
Page 96: Figure 3-14
Advertising
3-15
BUS INTERFACE UNIT
Figure 3-13. Typical Bus Cycle with Wait States
Figure 3-14. ARDY and SRDY Pin Block Diagram
ALE
S2:0
A19:16
AD15:0
READY
WR
CLKOUT
T1
T2
T3
TW
TW
T4
Valid
Address
Address
Valid Write Data
A1040-0A
D
Q
ARDY
BUS READY
CLKOUT
Rising
Edge
D
Q
Falling
Edge
SRDY
A1041-0A
Advertising
This manual is related to the following products: