Intel 80C188XL - Manual (Page 400)

Index-3
INDEX
Data sheets, obtaining from BBS, 1-5
Data transfers, 3-1–3-6
instructions, 2-18
PCB considerations, 4-5
PSW flag storage formats, 2-19
See also Bus cycles
Data types, 2-37–2-38
DI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32,
2-34
Digital one-shot, code example, 9-17–9-23
Direct Memory Access (DMA) Unit, 10-1–10-27
and BIU, 10-8
and CSU, 10-8
and PCB, 10-3
arming channel, 10-18
DMA acknowledge signal, 10-2, 10-22
DRQ timing, 10-20
examples, 10-22–10-27
HALT bit, 8-22, 8-23, 10-20
hardware considerations, 10-20–10-22
initialization code, 10-22–10-27
initializing, 10-20
interrupts, 10-8
generating on terminal count, 10-19
introduction, 10-1
latency, 10-21
modules, 10-8–10-9
overview, 10-1–10-10
pointers, programming, 10-10–10-14
priority
channel, 10-8–10-9, 10-19
fixed, 10-8–10-10
rotating, 10-10
programming, 10-17–10-20
arming channel, 10-18
channel priority, 10-19
initializing, 10-20
interrupts, 10-19
suspending transfers, 10-20
synchronization, 10-18
transfer count, 10-18–10-19
programming, pointers, 10-10–10-14
requests, 10-3
external, 10-4
internal, 10-6
software, 10-6
Timer 2, 10-6
selecting source, 10-17
synchronization
destination-synchronized, 10-5
selecting, 10-18
source-synchronized, 10-5
unsynchronized, 10-6
timed DMA transfer example, 10-22–10-27
transfers, 10-1–10-27
count, 10-7
programming, 10-18–10-19
direction, 10-3
rates, 10-21
size, 10-3
selecting, 10-14
suspending, 10-7, 10-20
terminating, 10-7
Direction Flag (DF), 2-7, 2-9, 2-23
Display, defined, A-2
Divide Error trap (Type 0 exception), 2-43
DMA Control Register (DxCON), 10-15
DMA Destination Pointer Register, 10-13, 10-14
DMA Source Pointer Register, 10-11, 10-12
Documents, related, 1-3
DRAM controllers
and wait state control, 7-5
clocked, 7-5
design guidelines, 7-5
unclocked, 7-5
See also Refresh Control Unit
DS register, 2-1, 2-5, 2-6, 2-13, 2-30, 2-34, 2-43
DX register, 2-1, 2-5, 2-36, 3-6
E
Effective Address (EA), 2-13
calculation, 2-28
Emulation mode, 11-1
End-of-Interrupt (EOI)
command, 8-21
register, 8-21, 8-22, 8-27, 8-28
ENTER instruction, A-2
ES register, 2-1, 2-5, 2-6, 2-13, 2-30, 2-34
Escape opcode fault (Type 7 exception), 2-44, 10-2
Exceptions, 2-43–2-44
priority, 2-46–2-49
Execution Unit (EU), 2-1, 2-2
Extra segment, 2-5