Intel 80C188XL - Manual (Page 198)

8-3
INTERRUPT CONTROL UNIT
8.2.1.1 Interrupt Masking
There are circumstances in which a programmer may need to disable an interrupt source tempo-
rarily (for example, while executing a time-critical section of code or servicing a high-priority
task). This temporary disabling is called interrupt masking. All interrupts from the Interrupt Con-
trol Unit can be masked either globally or individually.
The Interrupt Enable bit in the Processor Status Word globally enables or disables the maskable
interrupt request from the Interrupt Control Unit. The programmer controls the Interrupt Enable
bit with the STI (set interrupt) and CLI (clear interrupt) instructions.
Besides being globally enabled or disabled by the Interrupt Enable bit, each interrupt source can
be individually enabled or disabled. The Interrupt Mask register has a single bit for each interrupt
source. The programming can selectively mask (disable) or unmask (enable) each interrupt
source by setting or clearing the corresponding bit in the Interrupt Mask register.
8.2.1.2 Interrupt Priority
One critical function of the Interrupt Control Unit is to prioritize interrupt requests. When multi-
ple interrupts are pending, priority determines which interrupt request is serviced first. In many
systems, an interrupt handler may itself be interrupted by another interrupt source. This is known
as interrupt nesting. With interrupt nesting, priority determines whether an interrupt source can
preempt an interrupt handler that is currently executing.
Each interrupt source is assigned a priority between zero (highest) and seven (lowest). After reset,
the interrupts default to the priorities shown in Table 8-1. Because the timers share an interrupt
source, they also share a priority. Within the assigned priority, each has a relative priority (Timer
0 has the highest relative priority and Timer 2 has the lowest).
Table 8-1. Default Interrupt Priorities
Interrupt Name Relative Priority
Timer 0 0 (a)
Timer 1 0 (b)
Timer 2 0 (c)
DMA0 1
DMA1 2
INT0 3
INT1 4
INT2 5
INT3 6